In a receiver circuit arranged in an LSI that performs high-speed serial transfer, a serial-to-parallel conversion circuit (termed as parallel conversion circuit) that converts received serial data (termed as serial receive data) to parallel data and outputs the parallel data is provided. Assume that serial receive data, in which each symbol is formed for each consecutive N bits wherein N is a natural number equal to or more than two, is received by a conventional parallel conversion circuit, for example. In this circuit, an uncertain delay time associated with the N bits is present in a delay time resulting from parallel conversion processing (termed as a parallel conversion processing delay time) from when the serial receive data is received until when parallel data reconstituted for each symbol is output.
This phenomenon occurs in the parallel conversion circuit because, according to a timing of receiving the serial receive data, varies a phase difference between a timing of receiving the serial received data and then reconstituting the parallel data for each symbol and a timing of outputting the reconstituted parallel data to an inside of the LSI.
For this reason, this uncertain delay time is accepted as a design specification in a system including the parallel conversion circuit as described above, connected by high-speed serial interface.
In recent years, as seen in an IEEE1588-compliant application for performing high-precision time management or a PON (Passive Optical Network) system application for performing transmission time allocation with high efficiency, a demand for real-time characteristics of a network itself has increased. In systems that use an application which greatly demands the real-time characteristics as described above, a delay time involved in communication between the systems is measured, and the transmission time allocation or the like is performed, based on a result of the measurement.
JP Patent Kokai Publication No. JP-P-2005-295117A (Patent Document 1) discloses a technique capable of suppressing variations in the parallel conversion processing delay time. This technique is used when serial receive data with each symbol formed of 10 bits therein is received and converted to parallel data in synchronization with a comma code (synchronization pattern information). According to this technique, when a bit slip in a comma code (synchronization pattern information) occurs, adjustment is made on a period of a recovery clock, and variations in the parallel conversion processing delay time can be thereby suppressed.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P-2005-295117A